An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
BiCMOS circuitry provides speed improvements over standard CMOS circuitry. Such employs bipolar transistors in addition to CMOS field effect transistors. The speed improvement results from the much higher current that bipolar devices can provide in a smaller space. In typical prior art BiCMOS processes, additional masking steps are utilized in either a standard bipolar process or a standard CMOS process to add-in the complementary bipolar or MOS devices. Specifically in adding a bipolar device to a CMOS process, one or more of the bipolar sub-collector contact, base region or emitter region must be added to a CMOS flow. These additions typically involve from three to 5 additional masking steps and associated process complexity with etches, implants, and film depositions.
It would be desirable to reduce these process complexities and provide BiCMOS processes having reduced masking steps.